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ci : fix Models Backend Check by shortening the hrm_text fixture (#29744)
The fixture recycles its two blocks over 8 cache slots, so the fp16 error builds up past the 1e-4 NMSE bound on the Vulkan T4 and WebGPU jobs of Models Backend. Two l-cycles keep every branch of the cycle loop and halve the error.
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@@ -166,7 +166,7 @@ static gguf_context_ptr get_gguf_ctx(const llm_arch arch, const bool moe) {
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//n_vocab = 4096; // must be >= the hard-coded codec head size (3072)
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n_vocab = 3072; // TODO: should be 4096, but user code cannot get `n_vocab_out` yet [TAG_LLAMA_N_VOCAB_OUT]
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} else if (arch == LLM_ARCH_HRM_TEXT) {
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n_layer = 8; // 1 layer per stack x 2 h-cycles x (3 l-cycles + 1) cache slots
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n_layer = 6; // 1 layer per stack x 2 h-cycles x (2 l-cycles + 1) cache slots
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}
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uint32_t n_head_kv = n_head;
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@@ -384,10 +384,10 @@ static gguf_context_ptr get_gguf_ctx(const llm_arch arch, const bool moe) {
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}
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if (arch == LLM_ARCH_HRM_TEXT) {
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// 8 cache slots alias 2 physical blocks: 1 low-stack layer + 1 high-stack layer
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// 6 cache slots alias 2 physical blocks: 1 low-stack layer + 1 high-stack layer
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ms.add_kv(LLM_KV_HRM_LAYERS_PER_STACK, uint32_t(1));
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ms.add_kv(LLM_KV_HRM_H_CYCLES, uint32_t(2));
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ms.add_kv(LLM_KV_HRM_L_CYCLES, uint32_t(3));
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ms.add_kv(LLM_KV_HRM_L_CYCLES, uint32_t(2));
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}
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if (arch == LLM_ARCH_MAPLE) {
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